Chapter 1 : 1 Introduction
1.1 A Brief History
1.2 Book Summary
1.3 MOS Transistors
1.4 MOS Transistors as Switches
1.5 CMOS Logic
1.6 CMOS Fabrication and Layout
1.7 Design Partitioning
1.8 Example: A Simple MIPS Microprocessor
1.9 Logic Design
1.10 Circuit Design
1.11 Physical Design
1.12 Design Verification
1.13 Fabrication, Packaging, and Testing
1.14 Summary
1.15 Exercises

Chapter 2 : MOS Transistor Theory
2.1 Introduction
2.2 Ideal I-V Characteristics
2.3 C-V Characteristics
2.4 Nonideal I-V Effects
2.5 DC Transfer Characteristics
2.6 Switch-Level RC Delay Models
2.7 Pitfalls and Fallacies
2.8 Summary
2.9 Exercises

Chapter 3 : CMOS Processing Technology
3.1 Introduction
3.2 Silicon Processing
3.3 CMOS Technologies
3.4 Layout Design Rules
3.5 CMOS Process Enhancements
3.6 Technology Related CAD Issues
3.7 Manufacturing Issues
3.8 Pitfalls and Fallacies
3. Historical Perspective
3.10 Summary
3.11 Exercises
3.12 References

Chapter 4 : Circuit Characterization and Performance Estimation
4.1 Introduction
4.2 Delay Estimation
4.3 Logical Effort and Transistor Sizing
4.4 Power Dissipatio
4.5 Interconnect
4.6 Wire Engineering
4.7 Design Margin
4.8 Reliability
4.9 Scaling
4.10 Pitfalls and Fallacies
4.11 Historical Perspective
4.12 Summary
4.13 Exercises

Chapter 5 : Circuit Simulation
5.1 Introduction
5.2 A SPICE Tutorial
5.3 Device Models
5.4 Device Characterization
5.5 Circuit Characterization
5.6 Interconnect Simulation
5.7 Pitfalls and Fallacies
5.8 Summary
5.9 Exercises

Chapter 6 : Combinational Circuit Design
6.1 Introduction
6.2 Circuit Families
6.3 Circuit Pitfalls
6.4 More Circuit Families
6.5 Comparison of Circuit Families
6.6 Silicon-on-Insulator Circuit Design
6.7 Pitfalls and Fallacies
6.8 Historical Perspective
6.9 Summary
6.10 Exercises

Chapter 7 : Sequential Circuit Design
7.1 Introduction
7.2 Sequencing Static Circuits
7.3 Circuit Design of Latches & Flip-Flops
7.4 Static Sequencing Element Methodology
7.5 Sequencing Dynamic Circuits
7.6 Synchronizers
7.7 Wave Pipelining
7.8 Pitfalls and Fallacies
7.9 Case Study: Pentium 4 and Itanium 2 Sequencing Methodologies
7.10 Summary
7.11 Exercises

Chapter 8 : Design Methodology and Tools
8.1 Introduction
8.2 Structured Design Strategies
8.3 Basic Design Methods
8.4 Design Flows
8.5 Behavioral/Functional Synthesis Design Flow (ASIC Design Flow)
8.6 Programmed Behavioral Synthesis
8.7 Automated Layout Generation
8.8 Mixed Signal or Custom Design Flow
8.9 Additional Design Interchange Formats
8.10 Design Economics
8.11 Data Sheets and Documentation
8.12 Closing the Gap Between ASIC and Custom
8.13 Historical Perspective
8.14 Pitfalls and Fallacies
8.15 Exercises
8.16 Appendix I: CMOS Physical Design Styles
8.17 Appendix II: Logic Optimization

Chapter 9 : Testing and Verification
9.1 Introduction
9.2 A Walk through the Test Process
9.3 Reliability
9.4 Logic Verification Principles
9.5 Silicon Debug Principles
9.6 Manufacturing Test Principles
9.7 Design for Testability
9.8 Boundary Scan
9.9 Pitfalls and Fallacies
9.10 Historical Perspective
9.11 Summary
9.12 Exercises
9.13 Appendix I: MIL-STD-883

Chapter 10 : Datapath Subsystems
10.1 Introduction
10.2 Addition / Subtraction
10.3 One / Zero Detectors
10.4 Comparators
10.5 Counters
10.6 Boolean Logical Operations
10.7 Coding
10.8 Shifters
10.9 Multiplication
10.10 Parallel Prefix Computations
10.11 Pitfalls and Fallacies
10.12 Historical Perspective
10.13 Summary
10.14 Exercises

Chapter 11 : Array Subsystems
11.1 Introduction
11.2 SRAM
11.3 Special-Purpose RAMs
11.4 DRAM
11.5 Read Only Memory
11.6 Content-Addressable Memory
11.7 Programmable Logic Arrays
11.8 Historical Perspective
11.9 Summary
11.10 Exercises

Chapter 12 : Special-purpose Subsystems
12.1 Introduction
12.2 Packaging
12.3 Power Distribution
12.4 I/O
12.5 Clock
12.6 Analog Circuits
12.7 Pitfalls and Fallacies
12.8 Historical Perspective
12.9 Summary
12.10 Exercises

Chapter 13 - Appendix: Verilog
13.1 Introduction
13.2 Behavioral Modeling with Continuous Assignments
13.3 Basic Constructs
13.4 Behavioral Modeling with Always Blocks
13.5 Finite State Machines
13.6 Structural Primitives
13.7 Test Benches
13.8 Verilog 2001
13.9 Pitfalls
13.10 Example: MIPS Processor

Chapter 14 - Appendix: VHDL
14.1 Introduction
14.2 Behavioral Modeling with Concurrent Signal Assignments
14.3 Basic Constructs
14.4 Behavioral Modeling with Process Statements
14.5 Finite State Machines
14.6 Parameterized Blocks
14.7 Example: MIPS Processor